The present invention relates to electronic circuits, and, more particularly, to class D pulse width modulation (PWM) amplifiers.
FIG. 1 shows the typical scheme of a class D amplifier. This type of amplifier is a well-known PWM system (see K. Nielsen, xe2x80x9cReview and Comparison of PWM methods for analog and digital input switching power amplifiers,xe2x80x9d AES Mar. 22-25, 1997).
The operation of the amplifier is depicted in FIG. 2. The input signal (Vin) is compared with a waveform, most often triangular (Vtr) and having a relatively high frequency fsw much higher than the frequency band limit of the amplifier. The output (Vout) is a PWM signal switching between a positive voltage (Vcc) and a negative voltage (xe2x88x92Vcc). The average value (Vo) of the output digital signal represents an amplified replica of the analog input signal and may be easily calculated with the following equations:
Vo=Gxc2x7Vinxe2x80x83xe2x80x83(1)
                    G        =                  Vcc          Vtr                                    (        2        )            
where Vtr is the peak value of the reference (triangular) wave and G is the voltage gain of the amplifier.
The relationship between Vo and Vin is thereby theoretically linear. In practice though this is not true because the non-idealities of the triangular wave and the output buffer stage may produce an unacceptable amount of distortion on the output signal. Therefore, a feedback loop capable of compensating the non-idealities of the system is desired.
A typical feedback circuit is shown in FIG. 3. Given that the average charge of the integrating capacitor C must be null during a switching period (Tsw=1/fsw), it may be assumed that the average current on the feedback resistor R2 during a switching period is equal to the current on the input resistor R1, therefore:
Vo=Gcxc2x7Vinxe2x80x83xe2x80x83(3)
                              G          c                =                  1          +                                    R              2                                      R              1                                                          (        4        )            
where Gc is the closed loop gain of the system.
The open loop gain Cloop of the system may be easily calculated by analyzing the scheme of FIG. 4, wherein a linearized system is considered with the Vin node short-circuited to ground and the PWM stage substituted with a linear block with a gain Vcc/Vtr (see equation 2).
The input resistor R1 has been neglected because, at the frequencies of interest, the negative input of the integrator represents a virtual ground (because the integrating capacitor C provides an extremely low impedance) and therefore there is not any significative voltage drop on the input resistor R1.
The open loop gain Gloop and the unity gain frequency are thus respectively defined by:                                           G            1                    ⁡                      (            s            )                          =                              Vcc            Vtr                    ·                      1                          s              ·              R2              ·              C                                                          (        5        )                                          f          0                =                              1                          2              ⁢              π                                ·                      Vcc            Vtr                    ·                      1                          R2              ·              C                                                          (        6        )            
This system has a stability limit that limits the system""s bandwidth This limit may be calculated (referring to FIG. 3) by considering that for a correct functioning of the system, the slope of the ripple signal (Vr) must be lower than the slope of the triangular wave (Vtr). If this condition is not met, the system may produce repeated output switchings at intervals equal to the delay of the chain delay defined by the PWM stage and by the output buffer stage.
Correct and critical functioning conditions are schematically depicted in the diagrams of FIG. 5. By converting this concept into formulas:
Pt=4xc2x7Vtrxc2x7fsw (slope of triangular waveform)xe2x80x83xe2x80x83(7)
                              p          2                =                                            1              C                        ·                          (                                                ±                                      Vcc                    R2                                                  -                                  Vin                  R1                                            )                                ⁢                      xe2x80x83                    ⁢                      (                          slope              ⁢                              xe2x80x83                            ⁢              of              ⁢                              xe2x80x83                            ⁢              the              ⁢                              xe2x80x83                            ⁢              ripple                        )                                              (        8        )            
To obtain the limit condition the maximum slope of the ripple signal should be considered, that is, the maximum input signal Vinmax. From equations (3), (4):                               Vin          max                =                  Vcc          Gt                                    (        9        )            
Therefore, the maximum p2 value is given by:                               p                      2            ,            max                          =                                            1              C                        ·                          (                                                Vcc                  R2                                +                                  Vcc                                      R1                    ·                    Gt                                                              )                                =                                                    Vcc                C                            ·                              (                                                      1                    R2                                    +                                      1                                          R1                      +                      R2                                                                      )                                      =                                          Vcc                                  R2                  ·                  C                                            ·                              (                                  1                  +                                      R2                                          R1                      +                      R2                                                                      )                                                                        (        10        )            
Therefore, the limit condition is:                               p                      2            ,            max                          =                                                            Vcc                                  R2                  ·                  C                                            ·                              (                                  1                  +                                      R2                                          R1                      +                      R2                                                                      )                                      ≤                          4              ·              Vtr              ·              fsw                                =                      p            t                                              (        11        )            
Considering equation (6), this condition may be rewritten as:                               f          0                ≤                              2            π                    ·                      1                          (                              1                +                                  R2                                      R1                    +                    R2                                                              )                                ·          fsw                                    (        12        )            
which represents a bandwidth limit. It should be noticed that for a Ggain greater than 10 (that is for R2/R1 greater than 10), equation (12) may simplified into the following equation:                               f          0                 less than                   fsw          π                                    (        13        )            
Confronted with these limitations and drawbacks of known amplifiers, a manner has now been found to overcome this limiting critical condition and allow for an extended bandwidth at the expense of a negligible reduction of the range of variation of the duty cycle of the digital output signal.
The amplifier of the present invention functions even when the slope of the triangular wave is lower than the slope of the ripple of the input signal without causing spurious repetitive switchings of the output signal.
This important result is obtained by introducing a certain delay on the direct signal path, downstream of the PWM output stage, and in any case before the output node from which the feedback signal is derived for compensating the non-idealities of the system.